Asic Engineer Resume Samples

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G Windler

Giuseppe

Windler

639 Libby Dam

Los Angeles

+1 (555) 561 4962

639 Libby Dam

Los Angeles

Phone

p +1 (555) 561 4962

Experience Experience

San Francisco, CA

Asic Engineer

San Francisco, CA

Lesch-Ledner

San Francisco, CA

Asic Engineer

Performs other related duties as assigned
Drive Continuous Improvements of Products and Processes
Develop and Test High Quality Products
Strong technical foundation in optical networking
Perform Trouble Shooting and Customer Support
Excellent troubleshooting capabilities
Knowledge of Low Power design concepts (Power gating, Multi-Voltage, Retention, etc.)

Phoenix, AZ

Senior Asic Engineer

Phoenix, AZ

Fadel Group

Phoenix, AZ

Senior Asic Engineer

ASIC-PD Flow Automation Developer will develop software tools for NVIDIA's Timing Closure flows
Own micro-architecture and RTL development of assigned set of features in a high performance memory sub system
Develop and enhance timing analysis/signoff work flow from frontend (pre-layout) to backend (post-layout) at both chip and block level
Development of PD work flows.
Working among various engineering disciplines including hardware, firmware, software, system test and manufacturing
Develop custom timing scripts using tcl/primetime for clock skew analysis, special circuits such as clock dividers, core logic IO macros interfaces such as PCI-E, Frame-Buffer/Memory, HDMI, etc
Develop and implement techniques for power reduction in memory sub system

present

Houston, TX

Principal Asic Engineer

Houston, TX

McKenzie-Rau

present

Houston, TX

Principal Asic Engineer

present

Work with backend teams to address any layout and timing issues for ASICs
Work with STA engineer to ensure consistency of SDC/TCL constraints across the entire ASIC flow
Develop and maintain Power Optimization synthesis flows
Working with DFT Architect to incorporate Test Logic in Synthesis
Work with Signoff Engineers to sustain the correct Timing and Power margins
Own the CDC flow and work with RTL engineers to remedy Clock domain issues
System development and debugging

Education Education

Master’s Degree in Engineering

The Ohio State University

Master’s Degree in Engineering

Skills Skills

Knowledge in UVM desirable
Good communication skills. Ability to work as part of a team
Knowledge in SystemVerilog desirable
2-3 years of professional experience in design verification
Self-learning. Ability to work independently
Write verification environment in UVM (85%)
Experience with common serial protocols such as I2C, SPI, etc
Experience with embedded microprocessor / microcontrollers such as ARM or 8051
Experience with DFT and scan
Verification experience

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Senior Asic Engineer Resume Examples & Samples

Hardware test/verification environment and design is developed using a UVM framework with tightly integrated C++ modeling. You will use knowledge from your programming courses that include advance data structures, algorithms, and design patterns as well as languages such as Verilog HDL, and C++/perl/tcl/python
You will architecture test environments which include developing constrained random stimulus generators, automated response checkers, and advanced configuration and programming API components
Some of these components are reused across the entire phase of the project from module, chip and system level verification on Linux based verilog simulators all the way up to embedded applications running as part of the product's test features
Problem solving skills and out-of-the-box thinking to test and validate hardware designs as well as write reusable UVM/C++ classes for various simulation environments
Writing thorough and detailed specifications and test plans as well as oral descriptions will enable your ideas and concepts to be reviewed and accepted by other team members
4-10 years of related experience
BSEE is required/MSEE is preferred
Team-player, can-do attitude will work well in a group environment while still being able to contribute on an individual basis and you will find that you'll have lots of fun and thrive in this environment if you enjoy being challenged, learning new ideas, and push yourself to achieve aggressive technology goals

Senior Asic Engineer Resume Examples & Samples

Own micro-architecture and RTL development of assigned set of features in a high performance memory sub system
Micro-architect features to reach performance, power and area requirements
Work with HW architects to define critical features in memory sub system
Work with verification team to verify the correctness of implemented features
Develop and implement techniques for power reduction in memory sub system

Asic Engineer Resume Examples & Samples

Requires Master's degree or foreign equivalent in Electrical Engineering, Electronic Engineering, Computer Engineering, Computer Science, Communication Engineering, or related field and two (2) years of design experience in the areas of memory sub-system
Experience working in a network environment
Coaching & Mentoring Skills
Requirement analysis, design, integration, verification

Smts Asic Engineer Resume Examples & Samples

Development of upf (unified power format) design descriptions for multi-voltage domain SOC
Power rule checking for multi-voltage domain SOC designs using VC Static
Integration of AMD and third-party IP
RTL design in Verilog
RTL-based lint checking
Synopsys tool flow expertise
Synthesis with timing driven placement and design for power (DFP)
Static timing analysis and constraint development
Formal verification of synthesized netlists using Formality
Clock domain crossing (CDC) analysis using 0in
Principles of SOC, CPU, GPU microarchitecture and implementation
Bachelors of Science in Electrical or Computer Engineering and 3-8 years experience, or
Masters of Science in Electrical or Computer Engineering and 1-6 years experience, or
Doctor of Philosophy in Electircal or Computer Engineering and 0-3 years experience
Experience with Synopsys ASIC design tools (synthesis, simulation, equivalence checking, static timing analysis)
Understanding of ASIC design flow
Scripting, Linux/Unix environment
Strong organization and multitasking, as well as problem solving and analytical skills are a must
LS-SM1

Asic Engineer Clocks Resume Examples & Samples

Design new clocks modules in order to support high frequency clock with all the above constraints
Ability to design novel techniques to distribute clocks over long distances with low insertion delay, skew and OCV effects
Perform STA on the designed clock modules

Senior Asic Engineer Resume Examples & Samples

Co-work with architect to define module architecture/micro-architecture
Building for NVIDIA next generation IPs
Involved in the whole ASIC flow

Senior Asic Engineer Resume Examples & Samples

ASIC-PD Flow Automation Developer will develop software tools for NVIDIA's Timing Closure flows
These flows handle the automation of the timing closure and physical design of our large scale integrated circuits
A strong knowledge of object oriented programming in object oriented Perl and C++ is desired to take the tools to the next generation
Knowledge of timing closure, digital design, gate level Verilog netlist structures, and physical design concepts is required
This role will require interaction with project teams to support and improve the flow, and to provide regression and validation tests

Senior Asic Engineer Resume Examples & Samples

Define a comprehensive FV test plan
Formally specify design properties
Formally verify design properties using effective proving techniques
Develop Semi Formal Verification tools using in-house and vendor FV engines
Improve current verification methodology for more widespread FV deployment
Identification of formal verification application across existing projects

Asic Engineer Clocks Resume Examples & Samples

Design new clocks logics in order to support clocks & resets generation through complex sequence and high frequency clock and all the above constraints
Verify clock & reset logic and sequence, both for function and DFT mode, with the industry standard tools and methods at unit and system level to deliver high quality clock modules
Perform Synthesis & STA on the designed high speed clock modules

Principal Asic Engineer Resume Examples & Samples

10+ years of relevant experience. Degree in Electrical or Computer Engineering, graduate level or compensating experience
Fluent in TCL & PERL
Fluency in Verilog a must
Sound working experience with Physical Synthesis and MM-MC Corner Flows
Experience with Formal Verification ( Conformal) and Debugging Logical issues
Experience with Power Optimization and Power Analysis Tools PT/Tempus
Good understanding of mapping technology for sequential and combinatorial elements and the various tradeoffs
Working knowledge of SDC, TCL constraints and CPF/UPF

Asic Engineer Resume Examples & Samples

Experience in Verilog/VHDL RTL design
Knowledge of DFT, BSD and memory BIST
Knowledge of Cadence, Synopsys, Mentor EDA tools
Knowledge of Xilinx or Altera FPGA
C++/perl programming skill

Asic Engineer Resume Examples & Samples

Master’s degree in Computer Engineering, Electrical Engineering, or Computer Science
Coding in Verilog and/or System Verilog
Synopsys design compiler and prime time
Digital Circuit Design
Design for Test
Coding in Perl and TCL

Asic Engineer Resume Examples & Samples

Original design, design verification, design synthesis, static timing analysis or design modeling
Designing in Verilog and/or System Verilog
Our design activities are accomplished by a diverse cross-functional team and therefore require the candidate to demonstrate excellent communication and interpersonal skills
Masters degree in Computer Engineering, Electrical Engineering, or Computer Science
Experience with Perl, TCL, C++, Java, Verilog and/or System Verilog
Understanding of logic design concepts using hardware design languages
Internship or coursework experience in advanced verification theories using System Verilog, VMM, UVM
Experience running hardware design language simulators, synthesis and layout tools

Asic Engineer Resume Examples & Samples

Bachelor's Degree in Electrical Engineering. Desired: Master’s Degree in Electrical Engineering or equivalent experience
Must have 2 to 5 years experience developing VLSI logic blocks (specification, design, HDL implementation and verification/simulation)
Must be able to work independently and in a team environment plus possess good interpersonal skills
Ability to recognize and analyze problems then develop and implement solutions
Familiarity with ASIC/SoC design/verification methodologies
Ability to write clear microarchitecture documentation
Ability to write clear verification plan documentation
Experience with Verilog, System-Verilog
Experience with image processing and pixel processing pipelines for video/image capture or processing
Experience developing logic for mixed signal devices
Experience with Cadence DFII environment
Experience with DFT and scan

Principal Asic Engineer Resume Examples & Samples

Participate in all phases of ASIC / FPGA design Flow (Synthesis, Place & Route, and Timing Closure), as required
Bachelor of Science degree in engineering or math
15+ years of work experience
Previous work experience in computer or communication chip architecture
Masters degree in engineering or math
ASIC / FPGA / SoC System integration experience
Strong Silicon/ASIC design experience
One or more of the following - Networking, Wireless, Modem, video CODEC, Logic design experience
Experience with Verilog and System Verilog
Demonstrated ability to deliver a product from concept to production
Demonstrate the ability to work in a dynamic environment that includes working with changing needs and requirements
Strong software design and skills are preferred

Senior Asic Engineer Resume Examples & Samples

Implement ASIC / SoCs / FPGAs for multiple products, starting at the specification & design phase, continuing, through vendor down-selection, implementation, and validation. You will find innovation in performance, power and cost to build the best possible product
Work with backend teams to address any layout and timing issues for ASICs
Bring-up and validate ASICs and FPGAs in the lab
System development and debugging
8+ years of work experience in computer or communication chip architecture
Master’s degree in engineering or math
Experience with latest simulation and verification methodologies (OVM, UVM)
Experience with EDA tools such as HDL Synthesis (Synopsys DC), HDL simulators (VCS, Questa, IES), HDL Lint tools (Spyglass), FPGA tools (Xilinx Vivado, Altera Quartus II)
Previous work experience with generic IP blocks like ARM or DSP processor or ARM interconnect, cache memory
Team-player, can-do attitude, works well in a group environment while still being able to contribute on an individual basis, enjoys being challenged, learn new skills

Asic Engineer Resume Examples & Samples

Master degree in electrical engineering
Excellent know how in digital signal processing
Strong technical foundation in optical networking
Knowledge in modern modulation formats, forward error correction and signal processing algorithms
Excellent troubleshooting capabilities
Excellent written and verbal communication skills and presentation skills

Asic Engineer Resume Examples & Samples

Write verification environment in UVM (85%)
Verification experience
Knowledge in UVM desirable
Knowledge in SystemVerilog desirable
Good communication skills. Ability to work as part of a team
Self-learning. Ability to work independently
Good English. Ability to communicate in English, both verbally and in writing is a must
2-3 years of professional experience in design verification
BSEE or equivalent

Asic Engineer Resume Examples & Samples

Experience in ASIC verification using SytemVerilog
Experience in Constrained-random verification is a strong plus
Experience with verification methodology like OVM/VMM/UVM is highly desirable
Experience designing ASICs for networking protocols (Ethernet, FCoE) a plus
Strong problem solving and ASIC debugging skills
MSEE or BSEE is required

Senior Asic Engineer Resume Examples & Samples

Responsible for architecture, design, implementation and verification of logic
Ability to implement all aspects of the process flow from definition, high level design to synthesis, place and route, and timing and power use
Participates in defining and reviewing vendor capability, CAD flows, vendor libraries and processes, specifying of custom analog blocks, floor planning, timing, chip assembly, layout, design checking, design for test, design for manufacturability, foundry interfacing, test and production ramp-up
Responsible for developing automated ASIC and FPGA verification strategies using Verilog and high level verification tools (e.g. Testbuilder, System Verilog, etc)

Principal Digital Asic Engineer Resume Examples & Samples

Expert Digital ASIC Engineer
Design, simulate, and layout small families of standard cells for use in ROIC array design
Optimize clock and signal paths and buffer sizes
Design, layout, simulate, implement and test digital circuits and systems using VHDL/Verilog based RTL design flow (FPGAs/ASICs) and transistor level circuit design
Document and specify digital functions and systems
Design and program digital systems using microcontrollers and hybrid FPGA/CPU approach
Develop test procedures

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