ASIC / Layout Design Engineer Job Description
ASIC / Layout Design Engineer Duties & Responsibilities
To write an effective ASIC / layout design engineer job description, begin by listing detailed duties, responsibilities and expectations. We have included ASIC / layout design engineer job description templates that you can modify and use.
Sample responsibilities for this position include:
ASIC / Layout Design Engineer Qualifications
Qualifications for a job description may include education, certification, and experience.
Licensing or Certifications for ASIC / Layout Design Engineer
List any licenses or certifications required by the position: IP
Education for ASIC / Layout Design Engineer
Typically a job would require a certain level of education.
Employers hiring for the ASIC / layout design engineer job most commonly would prefer for their future employee to have a relevant degree such as Master's and Bachelor's Degree in Computer Engineering, Design, Computer Science, Electrical Engineering, Science, Electronics, Engineering, Computer, Logic, Communication
Skills for ASIC / Layout Design Engineer
Desired skills for ASIC / layout design engineer include:
Desired experience for ASIC / layout design engineer includes:
ASIC / Layout Design Engineer Examples
ASIC / Layout Design Engineer Job Description
- Write ASIC specific part of test plan
- Participate in making functional/technology based chip targets in timing, area, power
- Responsible for IP development and maintenance
- Involves collaboration on or assuming the responsibility for a specific project, or a definable portion of a larger project, process or client group
- Includes accountability for results in that area, and for communication of the status of interdependencies to management or senior design staff
- Develop infrastructure and environment for IP/SoC level design verification
- Developing Testbenches and Verification Components such as UVCs, models, BFMs, and Re-usable Verification Environments
- Overseas definition, design, verification, and documentation for ASIC development
- Responsible for multiple aspects in PD areas and provide technically leadership to the engineering team
- Aaccountable for project delivery
- Video coding and decoding design and DV experience is desirable
- Bachelor with 5+ yeas and Master with 3+ in Electrical or Computer Engineering
- Experience of display specific-interconnection protocols (DisplayPort, LVDS, VGA,HDCP, DVI, HDMI etc) is a plus
- Good at C/C++, Perl, familiar with SystemC, PLI, Makefile is a plus
- BS Degree in Electrical or Computer System Engineering or Computer Science (5 years experience)
- MS (0-2 Years Experience Relevant Industry Experience)
ASIC / Layout Design Engineer Job Description
- Test Planning, Implementation and Execution
- Develop System Verilog (UVM) or C/C++ testbench and verification components
- Understand the architecture of the graphics IP and functional block being designed
- Debug function/performance bugs of graphics IP
- Work with RTL designer to get a full deep insight on the design under test, develop stressful testplan
- Build testbench, Create testcase to ensure maximum coverage
- Understand the architecture of the system management unit design
- Understand the architecture of the DXIO IP and functional block being designed
- Build UVM test bench and monitors for DUT
- Deploy IP drop to SOC and support SOC verification
- Strong interpersonal skills for interaction with large team on multiple sites
- Have a strong emphasis on meeting program requirements regarding features and schedules
- Must be able to effectively manage concurrent work on multiple projects
- Understand system architecture & specifications
- Apply necessary verification methodologies to ASIC design, such as coverage, assertion, randomization, gate-sim , and achieve the verification goals
- Proficiency coding with Verilog, simulating with NCSIM or VCS, & synthesizing with Synopsys DC
ASIC / Layout Design Engineer Job Description
- The successful candidate will work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for central DFD IP
- Develop innovative architectural improvements to optimize performance per millimeter, performance per watt, and performance per byte
- Develop features to enhance visual quality and immersive environments
- Develop new features for use cases enabling entrance into emerging markets and build stronger positions in current markets
- Develop architectural and micro-architectural specifications
- Develop test, test plans, infrastructure to validate performance, power and software
- Conduct present tradeoff studies to select best methods in a timely fashion
- Review the design specs with design team for the design verification plan
- Create test plan, create test env., create tests based on the test plan
- Run/debug verificaton tests, clean up the env/test case issues
- Experience with SystemVerilog, OVM, perl, Design Patterns a plus
- Background and interest in computer graphics a plus
- Major in EE, CS or related, Master Degree experiences
- Knowledge on computer architecture and PCIe devices is preferred
- Good knowledge on verification methodologies like UVM is a big plus
- Master’s Degree in Electrical or Computer Engineering preferred
ASIC / Layout Design Engineer Job Description
- Individual will lead cross functional teams including IPs, SOC, CAD, EDA vendors, technology, and joint venture team to execute and deliver milestones for tapeout
- As SOC DV lead focus on design verification of Server chip including block and full chip from all aspect of DV including Infrastructure, Methodology, tools, functional / Performance / Power verification, verification testplan coverage analysis (code and functional), debugging, and provide technically leadership to the engineering team
- The successful candidate will report to the SOC DFX Manager and will have the following responsibilities
- Write and review verification test-plans
- Develop verification infrastructure, test-bench components and test-cases
- Participate in ATE bring-up and debug the DFT patterns on ATE and platform
- Work with global IP design team for FPGA/ASIC verification
- Focus on verification plan, debugging, test bench setup and coverage analysis
- The successful candidate will assume technical leadership of design verification for graphics pipeline
- Create test plan for complicated feature in GFX
- Proficiency coding with System Verilog & Verilog, and simulating with NCSIM or VCS
- Solid understanding of computer architecture principles, including pipelines and caches
- Familiar with Linux operating system, including debug tools
- Good working knowledge of UNIX/Linux and scripting languages
- Major in EE, CS or related, Master Degree with 3+ years or Bachelor with 5+ years working experiences in ASIC Company
- Co-coordinating design verification and implementation activities
ASIC / Layout Design Engineer Job Description
- Leading a small group of engineers to conquer challenging verification work
- Write tests in C, C++ and located bugs in simulation
- Work closely with architects and designers
- Co-coordinating across team in SoC or other IP during daily work
- Work in close collaboration with the front end designers and architects on the various SOC performace verification efforts
- Work with architects, and the design and DV team to develop functional and perfrormance Testplan
- Collaborate with analog designers to understand the circuit that the RTL is interacting with
- Analysis and debug of test failures
- The successful candidate will report to the SOC DFT (Design-For-Test) DV Manager and will have the following responsibilities
- Work with global Front-End design team and architect team for functional or performance verification verification for Graphics Chip
- For new college grads (less than 2 years experience), minimum GPA of 3.5 required for consideration
- Experience with perl or similar scripting languages
- Passion for ASIC validation
- BS (or MS) in EE, CS, CSE plus 2+ (or 0 with MS) years ASIC hardware design/verification experience
- Experience with Verilog, System Verilog required
- Experience with C/C++, SVA/PSL, and Perl a plus