ASIC Digital Design Engr Job Description
ASIC Digital Design Engr Duties & Responsibilities
To write an effective ASIC digital design engr job description, begin by listing detailed duties, responsibilities and expectations. We have included ASIC digital design engr job description templates that you can modify and use.
Sample responsibilities for this position include:
ASIC Digital Design Engr Qualifications
Qualifications for a job description may include education, certification, and experience.
Education for ASIC Digital Design Engr
Typically a job would require a certain level of education.
Employers hiring for the ASIC digital design engr job most commonly would prefer for their future employee to have a relevant degree such as Collage and Bachelor's Degree in Engineering, Applied Science, Communications, Management, English, Computer Science, Electronic Engineering, Computer Engineering, Design, Electronics Engineering
Skills for ASIC Digital Design Engr
Desired skills for ASIC digital design engr include:
Desired experience for ASIC digital design engr includes:
ASIC Digital Design Engr Examples
ASIC Digital Design Engr Job Description
- Participate in architecture design exploration, logic design and verification
- Participate in the implementation of firmware and system level algorithms using assembler
- Develop firmware scripts and firmware compiler
- Perform firmware validation using FPGA and Verilog simulations
- Understand design specifications
- Write behavioural models
- May perform logic synthesis and/or static timing analysis
- May perform mixed-mode simulations
- May participate in prototype evaluation using bench top laboratory instruments or automated test equipment
- May communicate directly with customers regarding technical support
- Strong working knowledge in of the following disciplines
- Requires a degree in Engineering or Applied Science (or equivalent)
- BSEE minimum, MSEE preferred
- Exposure to memory compilers will be a plus
- Exposure to FINFET technology nodes will be a plus
- Expertise in memory circuit design
ASIC Digital Design Engr Job Description
- Will contribute to technical review of RTL Code, VTB Code, etc of small and medium complexity
- The candidate should be able to analyze the coverage metrics and improve them with definition of additional test cases
- May need to interact with customers to discuss/ understand customers’ specification requirements, if needed for small and medium complexity
- Will contribute to technical review of TE Code of medium and large complexity
- Understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create micro-architecture and detailed design documents for some of the components of the Test Environment for the DesignWare family of synthesizable cores in protocol areas such as Ethernet/ USB/ SD, Multi-Media Cards/ AMBA (AMBA2, AXI)/ MIPI
- A minimum of 5-8 years of experience in ASIC design
- Hands-on experience in multi-core, cache coherency is a big plus
- Familiar with EDA tools such as, VCS, VERDI, SPYGLASS
- Writing directed verilog and possibly system-verilog test-benches
- Design and RTL implementation of domain specific processor hardware accelerators and related subsystem IP components
- Exposure to variation aware circuit design and analysis techniques
- Exposure to high speed and low power memory design
- Exposure to memory compilers will be a huge plus
- Exposure to FINFET technology nodes will be a huge plus
- Ability to lead a team of engineers towards execution
- The successful candidate will have preferred MSEE with at least 5 years of digital verification industry experience
ASIC Digital Design Engr Job Description
- Participate in the discussions and reviews of DFT to improve the correctness and efficiency of the DFT flow
- Study standard specifications published by JEDEC
- Define micro architecture at block level based on IP architecture
- Work on RTL design based on predefined coding style, SVA is also included
- Clean RTL check violations in lint, CDC, DFT and synthesis
- Run block level test to speed up IP verification
- Work with verification to debug and fix RTL issues
- Check synthesis timing and improve RTL design if required
- This is a position in leading edge IP Verification
- Develop and execute verification for IP level features related to Interface IP system
- Must have hands-on experience in writing complex testcases in Verilog and System Verilog
- Must have familiarity with code quality metrics
- Must have deep understanding of asynchronous clock crossings, DFT design methodologies, and synthesis implications of RTL
- Verification IP Development/Verification of IP Cores or SoC Designs for Set Top Boxes, Mobile handsets, Smart Devices
- Hands on experience in Verification IP or certain components of Test Environment coding, test case development and debug
- Bachelor’s degree in engineering is required with minimum 2 years of relevant experience in RTL functional verification
ASIC Digital Design Engr Job Description
- Participate in test environment and regression infrastructure development
- Participate in test cases development and debug
- He candidate will work in a project and team oriented environment with teams spread across multiple sites, worldwide
- Develop coreTools flow and automation tool set
- Write behavioural models and RTL code for circuit portions of integrated circuits
- This is a position in leading edge IP design
- Study specifications published by standard organizations such as IEEE, JEDEC and MIPI
- Define micro architecture based on IP architecture specification and standard specification
- Work on RTL design based on predefined coding style
- Insert SVA to ensure coverage
- Candidate should have a strong desire to learn and explore new technologies
- Demonstrates good analysis and problem-solving skills, can-do-will-do attitude
- Understanding of verification methodology such as UVM is a plus
- 1~3 years of related experience in either design or verification is preferred
- Master degree in E.E
- Capability to produce high quality technical documentation
ASIC Digital Design Engr Job Description
- Ensure RTL quality by check violations with Lint, CDC, Synthesis and DFT tools
- Develop and run block level tests to ensure fast convergence
- Work with verification team to debug and fix RTL issues and to reach both code and functional coverage goals
- Analyze synthesis timing and modify RTL design to improve timing if required
- To define verification strategy and verification plans based on high level specification
- Good debugging skills to clean up the design issues
- Able to Write testcases in Assembly, System Verilog, UVM
- Excellent grasp of Verification methodologies (System Verilog, OVM, UVM)
- Architectural definition of digital design IP functions
- Specification, development and verification of digital design IP functions
- Experience as FuSa engineer in safety critical applications with strong understanding of HW/SW development and functional lifecycle management
- ISO26262 working experience in qualifying systems with embedded HW and SW to ASIL levels A to D
- Functional Safety Certified Automotive Engineer (or equivalent) is a plus
- Hands on experience with System Verilog/ VERA coding and Simulation tools
- Bachelor’s degree in engineering is required as a minimum from a reputed college
- Minimum three years of experience in digital front end functional verification