Physical Design Job Description
Physical Design Duties & Responsibilities
To write an effective physical design job description, begin by listing detailed duties, responsibilities and expectations. We have included physical design job description templates that you can modify and use.
Sample responsibilities for this position include:
Physical Design Qualifications
Qualifications for a job description may include education, certification, and experience.
Licensing or Certifications for Physical Design
List any licenses or certifications required by the position: RCDD, VLSI/CMOS
Education for Physical Design
Typically a job would require a certain level of education.
Employers hiring for the physical design job most commonly would prefer for their future employee to have a relevant degree such as Master's and Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, Design, Engineering, Electronics, Science, Technical, Logic, Education
Skills for Physical Design
Desired skills for physical design include:
Desired experience for physical design includes:
Physical Design Examples
Physical Design Job Description
- Architecture evaluation and definition- Circuit Design Analysis and simulation
- Floor-planning and layout of the various RF/analog blocks
- You will be responsible for the layout and verification of your circuit blocks such as LNAs, mixers, amplifiers, VCOs, Power Amplifiers and other analog and RF circuits
- You would also create custom layouts such as inductor and baluns
- Verification includes running design rule checks DRC, schematic-to-layout verification LVS and debugging using standard industry tools
- Supports process improvement and development
- Support Factory Issues/Vendor Quality Issues
- Some interactions with management, vendors, factory to influence actions, purchases or alternative solutions
- Support project planning, feasibility and schedule estimating activities as needed
- Support/update and route both PCO & ECO for sheet metal design with minimal training and supervision in Creo 2.0
- Prior experience in timing closure, clock/power distribution and analysis, RC extraction and correlation
- Hands-on experience in full-chip/sub-chip Static Timing Analysis, timing constraints generation and management, and timing convergence required
- Expertise in physical design and optimization placement, routing, cell sizing, buffering, logic restructuring, to improve timing and power required
- Expertise in analyzing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron processes required
- Understanding of process variation effect modeling and experience in design convergence taking into account variations required
- Experience in critical path planning and crafting required
Physical Design Job Description
- Perform Ramp-up (lowpower) analysis for blocks/SubSystems and find out the best way to meet the ramp-up threshold
- Run Power EM, Signal EM and ESD checks using RedHawk
- RTL Power Analysis
- Clock-jitter analysis for a high speed block using RedHawk-PJX
- Perform IR drop analysis for a low power SoC with package layout included (using RHCPA)
- The successful candidate will assume technical leadership of a complex design generally including custom digital logic, an embedded u-controller and analog functionality
- Digital design and RTL coding for
- Expertise on high frequency clocking methodologies will be an added plus
- Implements ASIC backend design, including floorplan, placement, CTS, routing, parasitic extraction, STA, Power analysis, Xtalk analysis, physical verification and
- Basic understanding of CMOS VLSI IC design knowledge
- Successful track records of taping out complex, 65/40/28 nm SOCs
- Automation and programming-minded, solid coding experience in Makefile/Tcl/Tk/Perl
- Understands the big picture and detail oriented during execution
- Experience with DDR or CPU a plus
- Knowledge of logic design principles, physical design aspects power, timing and DFT concepts
- Familiar with typical SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions
Physical Design Job Description
- Basic logic/RTL design knowledge
- Basic skills in Linux, PC window setup
- Experienced with back-end ASIC design and integration flow knowledge is plus
- IP Physical implementation from RTL to silicon with design convergence
- Design Co-optimization from Architecture to Silicon process technology, collaterals, design methodology, architecture
- Product PPA Optimization and benchmarking of design styles, tools and methodology, silicon technology, collaterals libraries, memories, Floorplan vs architecture interdependencies
- Evaluation, development and optimization of Physical Design Recipes for internal and external IP's, including routing recipes, metal interconnect wire classes Lego's, clock implementation techniques, timing optimization factors, power optimization techniques
- Advanced Silicon Technology definition based on product requirements- Standard Cell Libraries and Memory Compilers benchmarking and definition based
- Identifies, defines, investigates and develops human centered design solutions to customer experience painpoints
- Influences cross-functional teams to develop effective design intent to promote the progress and success of projects
- Must be pursuing a Bachelors in Computer Science, Computer Engineering or Electrical Engineering
- BS/MS in ME, EE or CS
- Drive the block level's timing, DRC, LVS, FV convergence participate in the convergence for full chip
- Demonstrated knowledge of running performance analysis using STA Spice level circuit analysis
- Strong working knowledge of STA
- MS/PhD in CS/CE/EE
Physical Design Job Description
- Develop, script and optimize logic synthesis flows and block floorplans
- Drive block physical implementation through synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, ECO and sign-off
- Focuses on customer centricity using design methodologies that are focused on solving complex CX problems in an Omni Channel experience
- Partners with internal and external research groups to identify and investigate potential customer pain points or opportunities
- Communicates service concepts and ideas clearly, using methods, tools that illustrate the desirability, viability and feasibility of solutions
- Synthesize customer needs, business goals and technical capabilities
- Develop and contribute to concepts and visual design elements including typography, visual concept, logo, icon design and interactive platforms
- Test and refine prototypes with a view to refining them for delivery at pilot and scale
- Develop systematic and rigorous experience documents, including the definition of customer needs, task analysis, and the creation of personas, storyboards, scenarios, user flows and use cases
- Refine and continuously improve prototypes and final deliverables based on balancing customer experience objectives with Lowes business objectives
- Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation
- BS in Electrical or Computer Engineering + 3 yrs experience in Synthesis and Timing
- Good understanding of VLSI/Digital Integrated Circuits
- Good Scripting Perl/TCL background
- Some basic understanding of Physical Design Flow
- Comfortable working in a banking environment with a desk bound culture
Physical Design Job Description
- Mentor/guide/supervise other Physical Design Engineers and support cross-functional engineering effort to drive to signoff closure for tapeout
- Create scripts and tools as needed to be used by our memory design teams to improve productivity
- Create specifications for new tools and methodologies, lead the implementation, and validate enhancements made by our design automation team
- Interact, communicate, and collaborate with our various other internal teams to drive the development of the tools and flows
- Review existing processes and methodologies and identify areas for improvements
- Perform IC design rule and connectivity verification and drive products through mask release flows
- Contribute to methodology improvements to increase layout and verification efficiency
- Create reticle layouts, documentation, and PO’s to release products for mask build
- Complete PCB layouts for test hardware
- Work with developers to budget for and subsequently optimize timing, area and power
- Expertise in physical implementation & timing closure flow with hands-on experience in synthesis, formal equivalence, placement, optimization, low power checks, clock tree, routing, crosstalk delay/noise analysis & repair using Cadence/Synopsys/Magma tools
- Knowledge of commonly used clocking, low power schemes, spice simulations, DFT techniques are added advantage
- Knowledge of commonly used clocking, low power schemes, critical paths spice simulations, DFT techniques are added advantage
- A good working knowledge on Perl is required
- Previous experience on physical design and automatic place and route a plus
- Previous experience on custom layout and physical verification a plus